It is very important to make our designs free of any clock or data glitches to ensure correct functioning. Such cases need the attention of designer and needs to be fixed in design.įig 3.2 Glitch at converging paths through analog block The glitch may get sampled in the design and may lead to unexpected behavior. This kind of design which is purely combinational (with some hard macros) is always glitch prone. Consider a case where B toggles and A = 1 we may observe glitches at output of second AND gate. The output of second AND gate is fed back to Analog IP. Also there is another AND gate which has B and output of Analog IP as inputs. ![]() Refer to below design (Fig 3.2), here we have two inputs A and B which are combined through AND gate and fed to Analog IP. Such structures can easily be caught with any CDC tool or in GLS.ģ.2 Glitch at converging paths through analog block We may waive the below structure if all the other inputs to this combo logic are static when used. Here again designer needs to review all the paths at the interface. Also the glitch may get sampled in the destination domain and may lead to erroneous behavior. If such logic is present it may lead to a glitch. In an ideal situation, there should be no combinational logic present at CDC Interface. But there are cases ( described below ) where such timing parameters are not met and glitches may get sampled in the design.ģ.1 Use of combinational logic at CDC Path But since the timing parameters are met for each and every synchronous path, this glitch will not be sampled in the destination domain. Such cases need to be carefully reviewed and fixed in design after being caught by tool or GLS.įig 2.5 Using combinational gates for clock gatingĪny combinational logic used in data path is glitch prone. Also while using a CG cell there might be a case where enable is launched from a clock domain that is different from that of clock to be gated. One of them being usage of combinational gates (AND, NOR, XOR, etc.) and not CG cells for gating of clocks (Fig 2.5). There are other scenarios also that can lead to glitches in clock. We must ensure that we don’t have such structures in our design.įig 2.4 Clock signals reconverging on a mux In the below design (Fig 2.4), output of the mux after passing through the clock-pin of flip- flop/latches reconverge back on the same mux. This ensures that there is no asynchronous path from flop generating enable and clock gating cell. Refer to below design (Fig 2.3), If enable of a clock gating cell is coming from a flop which clears the enable signal asynchronously due to assertion of asynchronous reset (Func_rst) while the input clock is still active, can produce glitch at the output of the cell. Design solution for this is that the enable should be synchronized using 2-DFF structures which are either non – resettable flops or having POR as reset. Fig 2.2 Converging outputs of flops as clock
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